The minimum size of a Static Random-Access Memory (SRAM) cell is determined in part by the minimum pitch of the lithography used to manufacture the cell and in part by the variability in certain dimensions of the transistors (e.g. length of the gate), which contributes to variability in the overall performance of the entire cell. Spacer lithography processes for creating positive features such as lines have been demonstrated and are capable of providing a pitch below the limit of conventional lithography processes with little variation in thickness. However, in devices, such as SRAM cells, that require both positive features and negative features (ex. cut-lines, contact holes, etc.), the degree of integration capable when using positive spacer lithography is limited by the size of the negative features obtainable with conventional processes. As such, there is a need for a process for fabricating negative features at a substantially reduced size. There is also a need for a process of fabricating an SRAM cell at a size substantially less than that which is currently achievable.